This application claims priority to Japanese Patent Application No. 2000-253194 filed Aug. 23, 2000, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device such as, for example, an EEPROM (Electrically Erasable and Programmable Read-Only Memory) device.
2. Description of the Related Art
Conventionally, an EEPROM type memory device accumulates charges in a floating gate of a floating gate-type MOS transistor (hereinafter, referred to simply as a xe2x80x9ctransistorxe2x80x9d) forming a memory cell, and stores data using a change in the threshold voltage value of the transistor which is caused by a change in the amount of the charges accumulated in the floating gate. However, in actual use, a phenomenon occurs that the charges accumulated in the floating gate escape via an insulating layer provided for insulating the floating gate from an electrode of the transistor. Such a phenomenon occurs because, for example, the insulating layer deteriorates over-time, and generates a data storage defect.
In order to prevent this phenomenon, the following techniques are used in general: (i) the insulating layer of the memory cell is reinforced during the production process of the EEPROM type memory device; and (ii) the voltage conditions for erasing and writing data are optimized so as to minimize a stress applied to the insulating layer when data is erased or written.
One example of the techniques (i) and (ii) is described in Japanese Laid-Open Publication No. 8-190796 entitled xe2x80x9cFlash Memory Having Data Refreshing Function and Data Refreshing Method for Flash Memoryxe2x80x9d.
The above-mentioned publication discloses a method of detecting a memory cell, among a plurality of memory cells, in which charges have escaped from the floating gate and then rewriting data to the detected memory cell. According to this method, a reference cell for erasing and a reference cell for writing are used. When a memory cell is determined to be at a writing level using the reference cell for erasing, and when a memory cell is determined to be at an erasing level using the reference cell for writing, the memory cell is determined to be the defective memory cell in which charges have escaped from the floating gate.
In general, the escape of charges from the floating gate occurs most often among the defects involving the floating gate of an EEPROM type memory device. Other defects include an excessive increase in charges accumulated in the floating gate in the memory cell. By the above-described conventional method for detecting a memory storage defect, a cell in which the charges have been increased cannot be clearly distinguished from a cell in which the charges have escaped, and thus an increase in the charges is determined to be an escape of charges. In this specification, the defect that charges escape from a floating gate of a memory cell will be referred to as a xe2x80x9ccharge escaping defectxe2x80x9d, and the defect that charges are excessively increased in a floating gate of a memory cell will be referred to as a xe2x80x9ccharge increasing defectxe2x80x9d. The charge escaping defect and the charge increasing defect are both data storage detects.
In the case where no measure is taken against the charge escaping defect or the charge increasing defect, the following inconvenience occurs. The data storage characteristic of the memory device has a prescribed level immediately after the memory device is produced, but the insulating layer of the floating gate of the device tends to deteriorate as the device is used, especially as more and more data is erased from or written to the device. The level of data storage characteristic of the memory device is gradually decreased. In order to provide a memory device which is reliable for an extended period of time with certainty, it is necessary to accumulate a vast amount of know-how or expertise in terms of both designing and production, which is very difficult to realize.
According to one aspect of the invention, a non-volatile semiconductor memory device for allowing a data writing operation to, a data reading operation from, and a data erasing operation from a plurality of non-volatile memory cells is provided. The non-volatile semiconductor memory device includes a data comparison section for outputting a first comparison result obtained by comparing data read from each of the plurality of memory cells and data read using a reference element for reading, a second comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for writing, and a third comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for erasing; and a data storage defect detection section for detecting a data storage defect of a memory cell among the plurality of memory cell, based on the first, second and third comparison results obtained from the data comparison section.
In one embodiment of the invention, the data comparison section includes a reference element group including the reference element for reading, the reference element for writing, and the reference element for erasing; and a sensing differential amplification section connected to each of the plurality of memory cells, which are of an EEPROM type, at one input end of the section and also connected to the reference element group at the other input end of the section.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for writing, the data storage defect detection section determines that the memory cell has a charge escaping defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, the data storage detection section detects the data storage defect at least one of: during a non-selection period of each memory cell, during a blank period while normal data read is performed from each memory cell, and when power is turned on.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for writing, the data storage defect detection section determines that the memory cell has a charge escaping defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a record information storage section for storing, as record information, memory cell information corresponding to the charge escaping defect and memory cell information corresponding to the charge increasing defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a record information storage section for storing, as record information, memory cell information corresponding to the charge escaping defect and memory cell information corresponding to the charge increasing defect.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a data rewriting section for, when a memory cell among the plurality of memory cells has the charge escaping defect, performing a data rewriting operation to the memory cell.
In one embodiment of the invention, the data rewriting section performs the data rewriting operation when the memory cell returns from a super low power consumption mode to a normal power consumption mode.
In one embodiment of the invention, the data rewriting section performs the data rewriting operation when the memory device goes into the super low power consumption mode.
In one embodiment of the invention, the data rewriting section performs the data rewriting operation by supplying power from a backup capacitance section when the memory device goes into the super low power consumption mode.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a supply voltage monitor section for outputting a writing stop signal for stopping the data rewriting operation when the power supplied from the backup capacitance section becomes a prescribed level or lower.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a final address storage section for storing a final address of a final memory cell, among the plurality of memory cells, from which the data reading operation was performed for detecting the data storage defect. The data storage defect detection section uses the address stored in the final address storage section to resume detection of the data storage defect by performing the data reading operation using the final address.
According to another aspect of the invention, an information apparatus uses the above-described non-volatile semiconductor memory device for detecting a data storage defect of a memory cell.
As described above, according to the present invention, a data storage defect is detected based on a comparison result between the data read from a memory cell and data read from each of a reference element for reading, a reference element for writing and a reference element for erasing. Therefore, a charge escaping defect and a charge increasing defect can be clearly distinguished from each other. Thus, highly reliable data storage can be realized without entirely requiring a vast amount of know-how to be accumulated.
According to the present invention, a data comparison section can be easily and satisfactorily formed using a reference element group and a sensing differential amplification section.
According to the present invention, a memory cell having an abnormal or defective data storage characteristic is detected using a reference element for reading and a reference element for writing. Therefore, a charge escaping defect can be detected with high precision.
According to the present invention, a memory cell having an abnormal or defective data storage characteristic is detected using a reference element for reading and a reference element for erasing. Therefore, a charge increasing defect can be detected with high precision.
According to the present invention, whether the data storage is normally performed or not can be checked when the memory device is turned on. Usually when the memory device is turned on, a memory system including the memory device is provided with a delay period for stable start. This delay time period can be used to perform a background data rewriting operation. Thus, a difficult-to-obtain time period for the background rewriting operation can be obtained with certainty. A data storage defect can also be detected during a non-selection period of the memory device and a blank period while normal data read is performed from the memory cell.
According to the present invention, when a memory cell has a charge escaping defect, the data can be rewritten to the memory cell to compensate for the defect.
When the memory system returns from a super low power consumption mode to a normal power consumption mode, the memory system is usually provided with a delay period for stable return. According to the present invention, this delay period is used to perform a background data rewriting operation. Thus, a difficult-to-obtain time period for the background rewriting operation can be obtained with certainty.
When the memory system goes into the super low power consumption mode, the memory system is usually provided with a delay period for stable return. According to the present invention, this delay period is used to perform a background data rewriting operation. Thus, a difficult-to-obtain time period for the background rewriting operation can be obtained with certainty.
According to the present invention, the memory device has a built-in backup capacitance section such as a capacitor for obtaining energy required to perform a background operation in the super low power consumption mode. Therefore, the stable background operation is obtained, and the time period in which the stable background can be performed can be extended.
According to the present invention, when the supply voltage lowers to a prescribed value or lower, the data rewriting operation is stopped. Thus, the data rewriting operation can be performed more stably.
According to the present invention, information regarding a memory having a charge escaping defect or a charge increasing defect is stored as record information. A record information storage section can be formed using a dedicated memory which allows data to be written only once. By removing the information from the record information storage section later, information (e.g., parameters) which is important for development of a device having still higher reliability can be obtained.
According to the present invention, when a background reading operation for detecting a charge escaping defect or a charge increasing defect is interrupted, address information of the final memory cell which was scanned is stored in, for example, a work RAM area. When the background operation is allowed to be performed again, the address of the memory cell at which the background operation is to be started is determined based on the information. Thus, an efficient background reading operation can be performed. When power is turned off while a background reading operation for detecting a charge escaping defect or a charge increasing defect is performed, address scanning information is stored in, for example, an EEPROM area. When the power is turned on again and the background reading operation is resumed, the address scanning information up to the previous background reading operation can be read from the EEPROM area and the reading operation is started using the address at which the previous background reading operation was terminated. Thus, an efficient background reading operation can be performed.
Thus, the invention described herein makes possible the advantages of providing a non-volatile semiconductor memory device for clearly distinguishing a charge escaping defect from a charge increasing defect so as to realize highly reliable data storage relatively easily without entirely requiring a vast amount of know-how to be accumulated.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.